Journal of information, knowledge and research in electronics and communication engineering




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powerpluswatermarkobject6404986JOURNAL OF INFORMATION, KNOWLEDGE AND RESEARCH IN ELECTRONICS AND COMMUNICATION ENGINEERING

DESIGN AND ANALYSIS OF 1KB 6T SRAM CELL IN DEEP SUBMICRON CMOS TECHNOLOGIES


1 MR P.J.DALVADI, 2 MR. R .J.ACHARYA, 3 PROF. K.M.PATTANI


1 M.E.[Electronics & communication] Student, Department Of E&C, C.U.Shah College of Engineering and Technology, Wadhawan,Gujrat

2 M.E.[Electronics & communication] Student, Department Of E&C, C.U.Shah College of Engineering and Technology, Wadhawan,Gujrat

3 Asst. Professor, Department Of E & C Engineering, C.U.Shah College of Engineering and Technology, Wadhawan,Gujrat


pravindalvadi@yahoo.com,rahulacharya.ec@gmail.com,kunalpattani@gmail.com



ABSTRACT: VLSI industry is mainly concentration minimum power consumption and less area. The goal of this paper is to reduce power and area of Static Random Access Memory (SRAM). Here 1kb six-transistor (6T) SRAM cell is designed using deep submicron (65nm, 45nm) CMOS technologies. Then it is simulated using LTSPICE for checking its functionality, Total power dissipation, read access time and write access time. Compared to 6T SRAM cell of both deep submicron CMOS technologies, 45nm CMOS technology has 45% less power consumption and less area required due to reduced channel length of CMOS transistor compared to 65nm CMOS technology.

Keywords--6T SRAM cell, less power, read access time, write access time, 1kb, CMOS technologies



  1. Introduction

In today technological changes happening, there is a huge demand for finding out devices with low power. The demand of low power becomes the key of the VLSI designs rather than high speed, particularly in embedded SRAMs and caches [3]. In deep submicron CMOS technology, we scaled down channel length of CMOS transistor, so that area of CMOS transistor is less. If area reduced then automatically power is less consumption. A few critical circuits in a system not only affect the design metrics but may fail to operate in deep submicron technology. Hence the SRAM arrays are designed, analysed and checked for its design metrics in deep submicron CMOS technologies.

Six-transistor (6T) SRAM cell is shown in Fig 1. 6T SRAM cell consists of two cross-coupled inverters (M1-M3 and M2-M4) [1-3].





Fig 1.Six-transistor (6T) SRAM cell

Transistors connected to the bitlines are called access transistors (M5-M6). Transistors pull the cell values

to VDD are called load transistor (M3-M4), and the ones connected to ground are called driver transistors (M1-M2).

This paper review section wise as under as: Section II deals with 1kb SRAM structure, section III deals with Write/Read Operation of both SRAM cell, simulation and results are discussed in section IV. Finally the conclusion is given in section V.

  1. 1KB 6T SRAM CELL STRUCTURE

Fig 2 Shows 1kb 6T SRAM cell structure.




Fig 2.1kb 6T SRAM cell Structure

1kb SRAM structure has 32 rows and 32 columns of SRAM cell. Row indicates wordline of SRAM cell. Column indicates bitline of SRAM cell [4,6-7]. In figure has some other circuit like write driver circuit, precharger circuit, address decoder and sense amplifier, which has special function for the SRAM cell.

A: WRITE DRIVER CIRCUIT

The function of the SRAM write driver is to write input data to the bitlines when Write Enable (WE) signal is enabled; otherwise the data is not written onto the bitlines [1]. Only one write driver is needed for each SRAM column. The schematic of the write driver circuit is shown in Fig 3.





Fig 3. Write Driver Circuit

B: PRECHARGE CIRCUIT

The function of the precharge circuit in the 6T SRAM array is to charge the Bit Line (BL) and Bit Line Bar (BLB) to VDD [6, 14]. The schematic of the precharge circuit for the 6T SRAM array is shown in

Fig 4. The transistor M1 and M2 will precharge the bitlines while the transistor M3 will equalize them to ensure both bit lines within a pair are at the same

Potential before the cell is read.





Fig 4. Precharge Circuit


C: ADDRESS DECODER

Address decoder is used to decode the given input address and to enable a particular wordline (WL). In particular dynamic NAND CMOS decoder is used [9-12]. For an n-word memory, an m: n dynamic NAND CMOS decoder is used where m=log2n. The schematic of 2:4 dynamic NAND CMOS decoder is shown in Fig 5. 5:32 dynamic NAND CMOS decoder made for 1Kb SRAM cell. According to selection of input we can enable particular wordline row of SRAM structure. All the outputs of the array are high by default, with the exception of the selected row, which is low. Since the interface between decoder and memory often includes a buffer, it can be made inverting to enable the WL.




Fig .5 2:4 Dynamic NAND Decoder

D: SENSE AMPLIFIER

The function of SRAM cell in Sense amplifiers (SA) is sensing signal from BLB and BL. Sense amplifier is an important component in memory design. One of the major issues in the design of SRAMs is the speed of read operation. SA is present in every column of SRAM array [1, 6, 11]. Fig. 6 shows SA circuit for the 6T SRAM array. Using the approximate values, the simulations were run and the widths were optimized to get the best output. The read operation begins by precharging and equalizing both the bitlines, with simultaneously biasing the latch-type SA [12] in the high-gain meta-stable region by precharging and equalizing its inputs. And then to read a particular word from the SRAM array, the corresponding row is selected by enabling the WL. Once a sufficient voltage difference is built between the bitlines, the SA is enabled by read enable (RE) signal. The SA will sense which bitline is heading towards high voltage and which bitline is heading towards ground potential and then a full voltage swing is obtained at the output.




Fig 6. latch-type SA for 6T SRAM cell

  1. Write/Read Operation

Firstly the write operation of the cell is described as follows. Write operation means store data into the nod of SRAM cell. In order to store logic “1” to the cell, BL is charged to VDD and BLB is charged to ground and vise verse for storing logic “0”. Then the wordline voltage is switched to VDD to turn “on” the NMOS access transistors. When the access transistors are turned on, the values of the bitlines are written into Q and QB [2].

The read operation means data read from the SRAM cell. To read from the cell the bitlines are charged to ground instead of VDD and the wordline voltage is set to VDD to turn on the NMOS access transistors. The node with logic “1” stored will pull the voltage on the corresponding bitline up to a high (not Vdd because of the voltage drop across the NMOS access transistor) voltage level. The other bitline is pulled to ground. The sense amplifier will detect which bitline is at a high voltage and which bitline is at ground [6]. If the cell was storing logic “0” the voltage level of BL will be lower than BLB so the sense amplifier will output logic “0”. If the cell was storing logic “1” then the voltage level of BL will be higher than BLB then the sense amplifier will output logic “1”.

  1. SIMULATION AND RESULTS

The following configuration of SRAM arrays were designed and analysed using the Standard 6T SRAM Cell: (a) 1*1 (1 bit) (b) 16*16 (256 bit) (c) 32*32 (1 kb). Various configuration of SRAM structure were simulated using LTSPICE software in (65nm, 45nm) CMOS technologies. The functionality Write/read operation of 1*1 (1 bit) 6T SRAM cell in 65nm, 45n are shown in Fig 7 and Fig 8. The functionality Write/read operation of 16*16 (256 bit) 6T SRAM cell in 65nm, 45nm are shown in Fig 9 and Fig 10. The functionality Write/read operation of 32*32 (1kb) 6T SRAM cell in 65nm, 45nm are shown in Fig 11 and Fig 12.Show all the figures functionality of the SRAM cell write 1 – read 1 – write 0 – read-0. Following are the signals used in the simulation results: ‘pc’ corresponds to PC signal given to the Precharge Circuits; ‘wl’ corresponds to the WL signal of row in the SRAM array. This is the output of inverting buffer circuit; ‘we’ corresponds to the write enable signal given to the write driver circuits; ‘di’ correspond to input data bits; ‘lpc’ corresponds to the Precharge signal given to the Local Precharge circuits; ‘re’ corresponds to the read enable signal given to the sense amplifier circuits; ‘q’ correspond to storage node Q, ‘q1’ correspond to storage node QB of the SRAM. For the 256bit has first row selected in getting out result of column 0 and 15. For the 1kb has first row selected and getting out of column 0, column 15 and column 31.Accoring to CMOS parameter file VDD=1.1V (in 65nm CMOS technology) and VDD=0.9V (in 45nm CMOS technology).



Fig 7. 1*1Write /read operation of 6T SRAM cell in 65nm CMOS technology



Fig 8. 1*1Write /read operation of 6T SRAM cell in 45nm CMOS technology





Fig 9. 16*16 Write/read operation of 6T SRAM cell in 65nm CMOS technology



Fig 10. 16*16 Write/read operation of 6T SRAM cell in 45nm CMOS technology



Fig 11. 32*32 Write/read operation of 6T SRAM cell in 65nm CMOS technology




Fig 12. 32*32 Write/read operation of 6T SRAM cell in 45 nm CMOS technology

Access time is most important parameter for SRAM operation. Access time is nothing but propagation delay to getting proper SRAM operation. The Read Access time is the time measured from the point at which the RE signal reaches 10% of VDD to the point at which the output signal becomes +/- 10% VDD of the required logic value Sense amplifier required some time to sensing output from ‘BLB’ and ‘BL’. The Write Access time is the time measured from the point at which the WE reaches 50% of VDD to the point at which the storage node of the cell reaches 50% of VDD. SRAM required some time to stored value at node QB and Q. Read access times and write access time for 6T SRAM cells result show in table .1

1KB SRAM cell

65nm

CMOS

Technology

45nm

CMOS

Tech-nology

Read Access Time

304 ps

232.52 ps

Write Access Time

97.93 ps

87.42 ps

Table 1. Read Access Time and Write Access Time of 1 kb 6T SRAM cell


Power dissipation is mainly considerable parameter while designing any memory. Here we have used 65nm and 45nm CMOS Technology.

Power = ID avg * VDD

power dissipation of different configure 6T SRAM cells in 65nm CMOS technology result show in table 2, 45nm CMOS technology result shown in table 3.

CMOS Technology

Configuration

TDP



65 nm

1*1

37.4946 µw

16*16

696.4672 µw

32*32

1412.22 µw

Table 2. Power Dissipation of 6T SRAM Cell In 65nm CMOS Technology.

CMOS Technology

Configuration

TDP



45nm

1*1

20.73 µw

16*16

383.44 µw

32*32

768.00 µw

Table 3. Power Dissipation of 6T SRAM Cell In 45nm CMOS Technology

The total number of transistors used for various configurations of 6T SRAM cells has been tabulated as shown in Table 4. If we reduce the CMOS technology then we have scale down channel length of transistor. so that automatic reduce the area of CMOS transistor structure. So that 45nm CMOS technology has required less area compared to other technology.

Configuration

Total number of transistors

1*1

31T

16*16

2136 T

32*32

7402 T

Table 4. Total Number of Transistors


  1. CONCLUSION

1 kb 6T SRAM cell is designed in 65nm, 45nm CMOS technologies. Above all the result from we can conclude that smaller deep submicron CMOS technology is used less power consumption and less area required. Here 45nm CMOS technology has 45% less power consumption compared to 65 CMOS technology and also less area.

VI. REFERENCES

[1]Sandeep R , Narayan T Deshpande , and A R Aswatha, “Designand Analysis of a New Loadless 4T SRAM Cell in Deep Submicron CMOS Technologies”, Second International Conference on Emerging Trends in Engineering and Technology, ICETET-09..

[2]Jinshen Yang and Li Chen, “A New loadless 4-transistor SRAM cell with a 0.18μm CMOS technology”, Electrical and Computer Engineering, CCECE Canadian Conference, pp. 538 – 541, April 2007.

[3] Sreerama Reddy G.MP, Chandrashekara Reddy, ‘‘Negative Word Line Scheme Based Low Power 8Kb SRAM for Stand Alone Devices”, European Journal of Scientific Research

[4]James S. Caravella, “A Low Voltage SRAM for Embedded Applications”, IEEE Journal of Solid-State Circuits, vol. 32, no. 3, pp. 428 – 432, March 1997

[5] Yen-Jen Chang, Shanq-Jang Ruan, and Feipei Lai, “Design and Analysis of Low-Power Cache using Two-Level Filter Scheme”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 4, pp.568-580, August 2003

[6]Andrei Pavlov and Manoj Sachdev, “CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies”, Springer, 2008 .

[7]R. Jacob Baker, CMOS Circuit Design, Layout and Simulation, Third Edition, Wiley Publication, 1964

[8]Nestoras Tzartzanis, “High Performance Energy-Efficient Design”, p 89-119, Springer 2006.

[9]Jan.M.Rabaey, Anantha.P.Chandrakasan, and Borivoje Nikolic, “Digital Integrated Circuits”, PHI, 2003.

[10]Sung-Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits”, TMH, 2003

[11]Mohammad Sharifkhani, “Design and Analysis of Low-Power SRAMs”, PhD Thesis, University of Waterloo, 2006.

[12] Bharadwaj S. Amrutur “Design And Analysis Of Fast Low Power SRAMs” August 1999

[13]Ingvar Carlson, “Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors”, Master’s Thesis, Linkopings University, 2004.

[14]Andrei S. Pavlov, “design and test of embedded SRAMs”,phd thesis,waterloo,Ontario,Canada,2005.

[15] Tegze.P.Haraszti, “CMOS Memory Circuits”, Kluwer Academic Publishers, 2002


ISSN: 0975 – 6779| NOV 11 TO OCT 12 | VOLUME – 02, ISSUE - 01 Page



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